The present application relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present application relates to a method of manufacturing integrated circuits having transistors with elevated source and drain regions and high-k gate dielectrics.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors.
The ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension (shallow source and drain extensions) that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking capability of the silicon dioxide spacers.
As the size of transistors disposed on ICs decreases, transistors with shallow and ultra-shallow source/drain extensions become more difficult to manufacture. For example, a small transistor may require ultra-shallow source and drain extensions with a junction depth of less than 30 nanometer (nm). Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically downward into the bulk semiconductor substrate. Also, conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate.
The source region and drain regions can be raised by selective silicon (Si) epitaxy to make connections to source and drain contacts less difficult. The raised source and drain regions provide additional material for contact silicidation processes and reduce deep source/drain junction resistance and source/drain series resistance. However, the epitaxy process that forms the raised source and drain regions generally requires high temperatures exceeding 1000xc2x0 C. (e.g., 1100-1200xc2x0 C.). These high temperatures increase the thermal budget of the process and can adversely affect the formation of steep retrograde well regions and ultra shallow source/drain extensions.
The high temperatures, often referred to as a high thermal budget, can produce significant thermal diffusion which can cause shorts between the source and drain region (between the source/drain extensions). The potential for shorting between the source and drain region increases as gate lengths decrease.
In addition, high temperature processes over 750 to 800xc2x0 C. can cause dielectric materials with a high dielectric constant (k) to react with the substrate (e.g., silicon). High-k (k greater than 8) gate dielectrics are desirable as critical transistor dimensions continue to decrease. The reduction of critical dimensions requires that the thickness of the gate oxide also be reduced. A major drawback to the decreased gate oxide thickness (e.g.,  less than 30 xc3x85) is that direct tunneling gate leakage current increases as gate oxide thickness decreases. To suppress gate leakage current, material with a high dielectric constant (k) can be used as a gate dielectric instead of the conventional gate oxides, such as thermally grown silicon dioxide.
High-k gate dielectric materials have advantages over conventional gate oxides. A high-k gate dielectric material with the same effective electrical thickness (same capacitive effect) as a thermal oxide is much thicker physically than the conventional oxide. Being thicker physically, the high-k dielectric gate insulator is less susceptible to direct tunnel leakage current. Tunnel leakage current is exponentially proportional to the gate dielectric thickness. Thus, using a high-k dielectric gate insulator significantly reduces the direct tunneling current flow through the gate insulator.
High-k materials include, for example, aluminum oxide (Al2O3), titanium dioxide (TiO2), and tantalum pentaoxide (TaO5). Aluminum oxide has a dielectric constant (k) equal to eight (8) and is relatively easy to make as a gate insulator for a very small transistor. Small transistors often have a physical gate length of less than 80 nm.
Thus, there is a need for an integrated circuit or electronic device that includes transistors not susceptible to shorts caused by dopant thermal diffusion. Further still, there is a need for transistors with elevated source and drain regions manufactured in an optimized annealing process. Even further still, there is a need for elevated source and drain regions which are formed in a low thermal budget (low temperature) process. Yet further, there is a need for a transistor with elevated source and drain regions and a high-k gate dielectric. Yet even further, there is a need for a process of forming a transistor with elevated source and drain regions and a high-k gate dielectric in a low thermal budget process.
An exemplary embodiment relates to a method of manufacturing an integrated circuit. The integrated circuit includes a gate structure on a substrate. The substrate includes a shallow source extension and a shallow drain extension. The gate structure includes a gate conductor above a high-k gate dielectric. The method includes steps of: providing the gate structure on the substrate, forming a shallow amorphous region in the substrate, providing spacers on sidewalls of the gate structure, and etching the substrate to remove at least a portion of the shallow amorphous region. The method also includes steps of: providing an amorphous semiconductor layer above the substrate and over the gate structure, removing a portion of the amorphous semiconductor material to expose the gate structure, and forming a single crystalline semiconductor material from the amorphous semiconductor material and a remaining portion of the shallow amorphous region via a laser annealing process.
Another exemplary embodiment relates to a method of manufacturing an ultra-large scale integrated circuit including a transistor. The method includes providing a gate structure on a top surface of a substrate, providing a pair of spacers for the gate structure, depositing an amorphous semiconductor material above the top surface of the substrate, removing the amorphous semiconductor material to a level below a bottom surface of the cap layer, and crystallizing the amorphous semiconductor material. The gate structure includes a gate conductor and a cap layer. The amorphous semiconductor material is crystallized in an annealing process. The annealing process is prevented from overheating a high-k gate dielectric within the gate structure.
Yet another exemplary embodiment relates to a process of forming a transistor with elevated source and drain regions. The process includes providing a gate structure, providing an amorphization implant to a substrate, providing a spacer structure to the gate structure, depositing an amorphous semiconductor material above the substrate and the gate structure, and crystallizing the amorphous semiconductor material to form single crystalline material. The gate structure includes a high-k gate dielectric above the substrate.